Generally speaking, having an independent clock source introduces a number of issues. You now have two independent jitter sources so jitter is usually higher, it takes additional power and cost to drive two signals instead of one, and now synchronization and skew between clock and data lines is critical. Systems using independent clock signals tend to be low-rate and low-power applications where the signal can be a constant value for a "long" time like I2C. Then skew can be fairly large and still allow plenty of margin to capture the data, and there is no worry about a PLL free-running long enough to rail the oscillator or whatever. Simple hand shaking is enough to start acquisition and recover the bits. Signals like the data streams in networks and PCs are not normally set to a constant (static, DC) value except in power-down conditions; otherwise, an idle signal is still toggling but sending random ("nonsense") data so the clock and data recovery (CDR) circuits stay locked to the signal. And during normal operation encoding is used to "scramble" the data and make sure the bit stream is "busy"; that is, the run length of 1's and 0's is limited by design so there are never too many in a row, and the CDR circuit always has plenty of bit transitions to keep it happy (stay in synch).
Some RF systems, and probably others, use a dedicated LO ("clock") signal that is carefully buffered and distributed, often to multiple end points (e.g. phased-array radars). That is a far different application than sending bits around in an audio or computer system (typically point-to-point links rather than distributed systems).
FWIWFM - Don
Some RF systems, and probably others, use a dedicated LO ("clock") signal that is carefully buffered and distributed, often to multiple end points (e.g. phased-array radars). That is a far different application than sending bits around in an audio or computer system (typically point-to-point links rather than distributed systems).
FWIWFM - Don