This will reduce noise floor and jitter as well
It would be conventional to power any clock recovery circuits from their own, low noise supply. Anyway, input jitter stops at the DAC clock (provided you are using the DAC clock as system master clock, and using a data pull protocol, rather than a data push protocol).
But your other comments make little sense to me.
The digital side of the electronics is just that; digital. It involves relatively large swings, at high frequencies, generating a huge range of digital noise. In the early days of ASIC design, I had to use a tool to analyse the internal ground bounce of the chip, to ensure that the supply rails didn't actually cross (i.e. reverse the supply polarity) when the clock switched; that's how bad the noise was. A bit of noise from the power supply is going to have negligible effect. So a low noise PSU is unnecessary on the pure digital circuits (barring clock recovery, which isn't digital). You might want to power the PCM output buffers to the DAC from a quiet PSU, to reduce noise coupling to the DAC.
Since there will be some coupling between digital and analogue supplies in the DAC, there's an argument that you might want to power the digital side of the DAC from a low noise linear PSU. But, again, the noise generated by the internal digital signal swings will massively dominate this noise.
The DAC analogue section certainly needs a low noise linear PSU, as any PSU noise will bw coupled into the output signal.
Arguing that the CMRR of op amps means that you don't need to use a low noise linear PSU for the analogue is just perverse, given that you have suggested powering the digital electronics from such a supply. A high CMRR is good, but why not help things along with a clean PSU anyway? A low noise linear PSU is cheap enough, as it only needs to be low power.