Jitter is pretty boring as soon as it hits 'very good' range honestly. As soon as the worst offender spikes are at or under -120dB, they are already below audible jitter!! But if we want to make it a measurement contest here you go.
Fourth place, RME ADI-2 with its proprietary SteadyClock FS. Very clean, note lack of spikes entirely.
3d place, AK4118 receiver with good clocks as seen in the D70. Spikes visible due to very low noise floor.
(pretty sure this graph's comment was meant to say -120dB)
Second place, OKTO DAC8 with heavy ESS jitter suppressing using ASRC and once again good clocks. Two tiny blips.
First place goes to SMSL VMV D1. It has an Altera cyclone FPGA with sole purpose being reclocking, uses the same AccuSilicon clocks as the D70
-170dB at its lowest point, and very,
very clean looking at the replacement board (shown in blue).
But like I started off my post. This is measurebating to the extreme. NONE of all four have any excessive spikes at all! You can't hear this!!